Source and drain resistance studies of short-channel MESFETs using two-dimensional device simulators

A method for calculating the parasitic source and drain resistances in MESFETs using two-dimensional device simulators is discussed. The source and drain resistances are calculated using the power dissipation and the electron heating in the parasitic resistance regions of the device structure. The parasitic resistances are calculated as a function of both the gate and the drain bias voltages. The resistance calculation method for MESFETs has been applied to three semiconductor device simulators: a drift-diffusion method simulator, an energy transport method simulator, and a Monte Carlo particle method simulator.<
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