Impact of a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond

We propose a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek-alphabetic letter /spl Phi/, fabricated through the penetration of the gate electrode (=word line) which has been formed beforehand, and the formation of the channel plug inside the penetrating hole. The V/spl Phi/T provides the 4F/sup 2/ cell. The substantial simplicity of the V/spl Phi/T process contributes to the reduction in the number of process steps. The above two features result in the drastic reduction in total chip cost. Moreover, we demonstrate that the advantages on electrical properties of the V/spl Phi/T become more prominent with proceeding of scaling down. We have indicated that the V/spl Phi/T is a promising candidate for the gigabit DRAM in terms of size, cost, and performance.