A function-pipelined architecture and VLSI chip for MPEG video image coding

A function-pipelined architecture is presented for MPEG video image coding. Also, based on a 0.8 /spl mu/m SPDM CMOS technology, a VLSI chip has been designed and implemented for such an architecture. The chip consists of 43,066 transistors and has a die size of 6,673 /spl mu/m/spl times/5,260 /spl mu/m (or 0.36 cm/sup 2/). In the future, with such a VLSI chip, a coding processor will be developed for improving the performance of the MPEG video encoding system under development.