Systematic approach to ultra-wideband Low Noise Amplifier design in CMOS technology

A systematic approach to CMOS low noise amplifier design is presented. This Method uses a new input impedance matching technique based on LC Ladder Matching Networks. With This approach a LNA is implemented in ADS2006. Simulations results for 0.13 mum TSMC technology shows a very low noise figure less than 1.75 dB and power gain up to 20 dB in middle frequency. S11 and S22 are less than -7 dB and -10 dB in average respectively. This amplifier consumes only 8.846 mw power with 1 v supply voltage.