High performance configurable distributed hybrid memory in structured ASIC

Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is not applicable in traditional Structured ASIC design due to design complexity and area constraint. In this paper, we presented a novel distributed memory architecture for Structured ASIC, Hybrid RAM (HRAM). It is built using HCell [1], the Altera HardCopy Structured ASIC logic cell. It is hybrid because it provides the advantages from both block RAM and distributed RAM. The HRAM also created using an innovative hybrid flow which is the combination of conventional custom design flow and ASIC design flow [2]. The implementation strategy will be shown in details and also various advantages for the HRAM architecture will be addressed in this paper.