Design and Optimization of 40V, 0.18μm versatile HVL-DMOS device with DOE

In this paper, a 40 V versatile HV LDMOS technology with lower R
_dson
has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical layout dimensions and implantation scheme. The optimized condition from DOE model provides good breakdown voltage with low R
_dson
, the values are BVDSS ~77 V & ~59 V; R
_dson
mu 84 mOmegamm
²
& mu192 mOmegamm
²
for n-LDMOS p-LDMOS respectively. Final tuning of the process & layout done by splits to improve the other device parameters such as leakage current, substrate current for better reliability & etc.