Impact of runtime leakage reduction techniques on delay and power sensitivity under effective channel length variations

As the fabrication process technology has moved from submicron to deep submicron region, it has become essential to minimize the leakage power and the variability of the design parameters such as delay and leakage. Although dual-V
_t
approach has been proposed for runtime leakage power reduction significantly without compromise in performance, it suffers from the limitation of complex fabrication process and higher sensitivity to process parameter variations with consequent effect on parametric yield. In this paper we have proposed a novel approach, which combines judicious use of sizing and an optimal single-V
_t
to achieve leakage power reduction comparable to that of dual-V
_t
, but less sensitive to process parameter variations, which has been established by extensive Monte-Carlo simulation experiments.