An integrated system for assigning signal flow directions to CMOS transistors

Signal flow direction information has been used to improve the accuracy and performance of many CAD tools. Hence deriving this information correctly and efficiently is an important and useful task. In this paper, an integrated system for deriving signal flow direction information in CMOS circuits is presented. This system consists of two subsystems: structure-based and rule-based. In the structure-based subsystem, a new graph-theoretic algorithm is used. The direction assignment problem is modeled as a two-paths problem on an undirected graph, called the global source target graph (GST-graph). The GST-graph is decomposed into split components by a linear time algorithm and the direction information of most edges in each split component can be derived by another linear time algorithm. If all transistors in a circuit are structurally unidirectional then their directions will be determined in this subsystem. Those transistors, if any, whose directions cannot be determined by this subsystem will be dealt with in the rule-based subsystem. A new set of rules including logic implication and precharge node driven rules have been developed. By considering circuit semantics, some difficult circuits such as a pass transistor based XOR gate, a six-transistor memory cell, barrel shifters, and precharge logic circuits can be processed. Experimental results show the accuracy and efficiency of this integrated system.