GEWE-RC MOSFET: A solution to CMOS technology for RFIC design based on the concept of intercept point

In this paper, the linearity performance of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET is investigated using ATLAS device simulator, based on the concept of intercept point. Further, the impact of various technological parameter variations, such as gate length (L
_G
), negative junction depth (NJD), screening metal gate workfunction (Phi
_M2
) and substrate doping (N
_A
) on the linearity performance of GEWE-RC MOSFET, has been explored. Simulation results reveal that GEWE-RC MOSFET design exhibits significantly improved linearity characteristics, in comparison to the conventional Recessed Channel (RC) and bulk, based on third-order input intercept power (IIP3) desirable for RF and wireless communication designs.