Hypercube multiprocessors with bus connections for improving communication performance

A modified hypercube with multiple buses used as bypass routes is proposed. This is achieved by partitioning all processor elements into subsets using coding theory and by connecting all PEs in each subset to a bus. The basic structure for small systems reduces the diameter to two (one on a bus plus one on a link). In the generalized structure for large systems, it is reduced to less than about one-third that of the regular hypercube.<
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