Simulation and analysis of enhanced switch architectures for interconnection networks in massively parallel shared memory machines

Improvements in performance which can be obtained by adding buffers to a crossbar switch are assessed by changing the configuration of the buffers and by adding the capability of combining messages to the buffers. Four basic k*k crossbar switch types are described: unbuffered; k-input buffers, one per output port; one-input buffers, one per input port; and one-input buffers, k buffers per output port. Previous analytical work and simulation studies of some of these switch types are reviewed, and the analysis is extended to the other types. An analytical model for simple hot-spot traffic is presented, and simulation results are shown for different kinds of message combining.<
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