A Chaos-based Image Encryption ASIC Using Reconfigurable Logic

This paper proposes an ASIC implementation of a chaos-based image encryption algorithm, which features dual-RAM connection and reusable data-path for each round of encryption and decryption. Within a pixel block, general cat-map and Logistic map are alternately used for permutation, diffusion and substitution. The algorithm is robust to many forms of attacks, and the proposed hardware structure bears good reusability. Experimental results show that when system frequency is 100MHz, the data throughput under 4 rounds of encryption and decryption reaches 4.98Mbytes/Sec and 4.66Mbytes/Sec respectively. Based on 0.18um standard cell library, the layout related information of the proposed ASIC is given.