Gate-level dual-threshold total power optimization methodology (GDTPOM) principle for designing high-speed low-power SOC applications

This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology, has a 24.6% reduction in total power consumption.