A novel H.264 QP adaptive MPDC block-matching algorithm and its VLSI design

The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4X4 integer transform and 52-level scalar quantization and the calculation process was adjusted for hardware optimization. When QP is greater than 18, the proposed criterion performs as well as SAD scheme, and the RDO curve error is less than 0.3 dB. Verilog HDL and SYNOPSYS DC-Shell are used for its VLSI design and implementation, and the synthesis results show that its 4 X 4 block-parallel structure saves 58% area and 77% power comparing with that of SAD’s at 200MHz. It is useful for some high-compression-ratio, low-cost and low-power video codec VLSI solutions.