Development of passive devices in 130 nm RFCMOS technology and PDK implementation for RF VCO designs

This paper focuses on the design of RF component design such as MOSFETs, varactors, capacitors and inductors in SMIC 0.13 ¿m RFCMOS technology. Modeling results of these passives devices and associated PDK are implemented in a 0.13 ¿m RFCMOS VCO design. The RF building block has been fabricated from 130 nm CMOS technology and achieved a phase noise of -140.8 dBc/Hz@1 MHz at a current consumption of 14 mA.