Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method

This paper studies various double-gate (DG) FinFET structures optimized for better ¿off state¿ and ¿on state¿ performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20 nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on I
_on
of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman design of experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET device¿s electrical performance.