The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm node and beyond

In this work, the impact of strain engineering on device performance and reliability for FUSI-gate SOI CMOSFET was investigated. With electrical measurement and reliability inspection, we found that there is similar enhancement on device performance, but different endurance on stressing induced device degradation for n/p MOSFET in respectively. Related noise analysis as well as charge pumping techniques were employed on the investigation of strain induced oxide defect which will accelerate device degradation after long time hot carrier stressing and/or bias instability stressing. And for manufacturability issue, a simple FUSI-metal-gate process with a fully compatible ultimate spacer process (USP) strain engineering is proposed for the first time. We found that channel mobility can be enhanced efficiently with about 28% and 40% I
_ON
gain by the tensile-stress and compressive-stress CESL for n/pMOS, respectively.