Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA

We present algorithms for implementing large-scale regular expression matching (REM) on FPGA. Based on the proposed algorithms, we develop tools that first transform regular expressions into corresponding non-deterministic finite automata (RE-NFA), then convert the RE-NFA into structural VHDL that utilize both logic slices and block memory (BRAM) available on modern FPGA devices. An n-state m-character input regular expression matching engine (REME) can be constructed in O (n times m log2 m) time using O (n times m) memory space, resulting in a circuit that occupies no more than O (n times m) slices on FPGA. A large number of REMEs are placed automatically onto a two-dimensional staged pipeline, allowing scalability to hundreds of REMEs with linear area increase, running at over 300 MHz on Xilinx Virtex 4 devices.