Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds

In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults.<
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