A built-in quiescent current monitor for CMOS VLSI circuits

A built-in I/sub DDQ/ monitor for CMOS digital circuits with low power supply voltage perturbation is presented. It minimizes the extra delay of the CUT in normal operation. An automatic recovery mechanism limits the drop in VDD voltage during the testing phase so the data storage is not perturbed. The I/sub DDQ/ current level may be measured by a standard digital IC tester. The performance parameters are compared with other published circuits and experimental results of an ASIC with the proposed BIC monitor are discussed.<
>