Direct performance-driven placement of mismatch-sensitive analog circuits

A new approach towards performance-driven placement of analog integrated circuits is presented. The performance specifications directly drive the layout tools without intermediate parasitic constraints. A simulated-annealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance specifications. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with a practical circuit example.<
>