An efficient conflict-free parallel memory access scheme for dual-butterfly constant geometry radix-2 FFT processor

In this paper, a parallel access scheme for dual-butterfly constant geometry radix-2 Fast Fourier Transform (FFT) algorithm is proposed. According to the constant geometry, the proposed method in this paper utilizes the Least Significant Bit (LSB) and the Most Significant Bit (MSB) of the data counter to decrease the computational complexity of the address generation for reads and writes. It allows simultaneous access to the 4 operands needed for the dual parallel butterfly calculations, so it only costs (N/4)*log
₂
(N) clock periods for calculating a N complex point radix-2 FFT or IFFT in hardware implementation. For every stage has the same architecture, it also enhances the implement flexibility of the FFT algorithm.