Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip

This paper describes the implementation of the slot synchronization of a W-CDMA receiver on a reconfigurable system. The system includes a general-purpose processor core with floating-point capabilities and a reconfigurable array. We mapped a 256-element correlation on the array and we evaluated its performance. The slot synchronization uses a large number of this correlations. The stand-alone correlation produces a speed-up of 70X when mapped on the reconfigurable core in comparison with the software implementation on a general-purpose RISC core. The slot synchronization based on this implementation gives a speed-up of 33X against an area overhead of 4X.