Design of High-Speed Charge-Pump in PLL

The phenomena of charge injection, clock feedthrough and charge sharing in charge pump are analyzed. A novel structure of charge pump for high-speed phase-locked loop is presented. The charge pump is designed with the Chartered 0.35 mum CMOS technology, and simulated with Eldo which is the analog circuits simulation tool of Mentor Graphics. Under 3.3 V DC supply voltage, the power consumption is 0.447 mW. The result of simulation shows that the circuit has an excellent performance for high-frequency applications.