Correlation of PDN impedance with jitter and voltage margin for high speed channels

Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.