Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.