A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GS/s at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of 1GS/s, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW, of power. The measured INL and DNL were within − 0.5LSB, − 0.7LSB, respectively. The measured SNDR, was 33.82dB, when the fin=100MHz at Fs=500MHz. The active chip occupies an area of 0.27mm
²
in 0.18μm CMOS technology.