1/5 power reduction by global optimization based on fine-grained body biasing

A fine-grained body bias control to compensate both the process and design variations is proposed. A test chip was fabricated in 90nm CMOS process. The proposed global optimization scheme reduced power by 23% compared with an as-fabricated chip power and by 11% compared with the power optimized by the conventional local optimization approach. Also, the proposed global optimization scheme reduced power by 19% compared with an as-fabricated chip power within 20 test iterations with simulated annealing algorithm.