Tessellation-enabled shader for a bandwidth-limited 3D graphics engine

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. By utilizing operational characteristic of tessellation, the TES is implemented with 6.2% additional logic of a dedicated unit based on a conventional vertex shader. With optimization of key components of a shader, a symmetric dual-core TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.