Characterization of the Back Interface in Strained-Silicon-on-Insulator Channel and Enhancement of Electrical Properties by Heat Treatment

The electrical characteristics of thin strained-silicon-on-insulator (sSOI) wafers were evaluated, and the effects of annealing processes on the back interface states of sSOI wafers were analyzed by using the back-gated (BG) metal-oxide-semiconductor field-effect-transistor structure. The electrical characteristics of the BG MOSFET fabricated on sSOI wafers were superior to that of conventional SOI wafers. However, the rapid thermal annealing (RTA) process induced significant degradations by increasing the back interface states between the strained-Si thin channel and the buried oxide layer. On the other hand, the conventional furnace annealing process at 500
^deg
C in a nitrogen (N
₂
) ambient was effective for reducing the RTA-induced back interface states, and the performances of the BG sSOI MOSFET annealed in N
₂
ambient were significantly improved.