Realizing reconfigurable mesh algorithms on softcore arrays

The reconfigurable mesh is a very popular model for massively parallel computation for which a large body of algorithms with exceptionally low runtime complexities exists. However, these low complexities can not be exploited due to the unrealistic assumption that communication time is either constant or logarithmic in the number of cores. Nevertheless, studying the reconfigurable mesh model and associated algorithms might lead to new approaches for the design and programming of many cores with light-weight, circuit-switched interconnects. In this paper, we present the mapping of reconfigurable mesh algorithms to softcore arrays. We first discuss our architecture and the corresponding tool flow, and then turn to the most critical issues, minimizing communication delay and establishing synchronization in the single-operand, circuit-switched network. We show experimental results from an FPGA prototype and evaluate our architecture by a sparse matrix multiplication case study.