A single-channel 10b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding

A 10b 1GS/s ADC employing a single channel cascaded folding architecture is presented. Conversion speed of 1GS/s is attained by incorporating low-power distributed track-and-hold amplifiers after each folder. This ADC achieves a record 55.6dB peak SNDR and a 64dB peak SFDR and sustains a latency of one clock cycle. DNL and INL at 1GS/s sampling rate are measured 0.4LSB and 1.1LSB. Fabricated in a 0.35μm BiCMOS process, the ADC consumes 2W from a 3.5V supply.