A 5-Gbps FPGA prototype of a (31,29)2 Reed-Solomon turbo decoder

In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra high-speed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus, a full-parallel turbo decoding architecture dedicated to the (31, 29)
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RS product code has been designed and then implemented into a 5 Gbps experimental setup. The purpose of this prototype is to demonstrate that RS turbo decoders can effectively achieve information rates above 1 Gbps. The results show that the RS turbo product codes offer a good complexity/performance trade off for ultra-high throughputs. The major limitation in terms of data rate of our prototype is the data exchange between the FPGAs of the board. Indeed, the turbo decoder architecture enables decoding at information rates until 10 Gbps onto FPGA devices.