High speed area efficient configurable Viterbi Decoder for WiFi and WiMAX systems

In this paper, an area efficient configurable design for high speed Viterbi decoder suitable for IEEE 802.11 based wireless LAN and IEEE 802.16e based WiMAX has been proposed. This design also supports the puncturing schemes defined in the above wireless standards. An area efficient VLSI design for trace back unit has been proposed in this paper. Synthesis results targeting FPGA and ASIC are included. These results show that the new architecture can achieve good speed, while offering significant area advantage.