A parallel implementation of MP3 decoding algorithm on Reconfigurable Computing systems

This paper describes a Reconfigurable Computing system, which consists of a general-purpose ARM processor and Reconfigurable Cells Array (RCA). A novel mapping mechanism which makes data-parallelism instructions operate on RCA has been proposed to map and implement MP3 audio decoding algorithm containing intrinsic data-parallelism operations. The communication interface between ARM processor and RCA is implemented efficiently using the standard ARM assembly language. With the standard ARM C Compiler, the hybrid decoding source files in which assembly language embedded are compiled to standard ARM machine instructions. The average decoding time of each frame is improved to 17.9ms, and enhanced approximately 10% to [1] which decoding time per frame is 20ms, when the sampling frequency and bit-rate are 44.1KHZ and 128kbps, respectively.