PHAFS: A parallel hardware accelerator for switch level fault simulation

Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. An overview of the PHAFS architecture and system is presented. The PHAFS hardware component uses a massively parallel SIMD (single instruction, multiple data) architecture based on an application specific integrated circuit to perform two-dimensional parallel switch level fault simulation up to 32 switches and 192 faults.<
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