Contact technology for high performance scalable BiCMOS on TFSOI

A selective W contact layer is deposited on both poly and silicon electrodes to realize scalable, high performance TFSOI BiCMOS. A unique double spacer integration results in high performance MOS and bipolar operation while providing adequate separation between poly and silicon electrodes to prevent sidewall leakage. Switching speed more than twice that of comparable bulk circuits is demonstrated. Limitations imposed by conventional silicon- and metal-diffusing self aligned silicides (Ti and Pt) are described. Pt silicide limits scaling of the spacer width while Ti silicide limits scaling of the silicon thickness. Selective W is shown capable of maintaining good device and circuit performance while not imposing such limitations.<
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