Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes

Behavioural modelling and yield optimization of resistor string based (potentiometer) digital-to-analog-converters (DACs) is presented to improve its reliability and area efficiency with focus on nonideal nanoscale CMOS processes, which suffer from large device tolerances. The optimization potential in terms of yield is analyzed taking systematic and statistical properties into account. Measurements of 4096-step and 16384-step DACs using 65 nm and 180 nm CMOS process show outstanding accuracy performance and excellent matching to simulated circuit performance using the behavioural model. Guidelines for efficient resistor string based DAC-design are presented.