Partitioned reuse cache for energy-efficient soft-error protection of functional units

With aggressive technology scaling, soft errors (changes in logic state arising from single-event transients due to radiation or electrical noise) are becoming a serious concern in logic circuits. Existing soft-error rate (SER) reduction schemes, which use explicit hardware and/or temporal redundancy, have significant power overheads and are impractical in systems where power is a key design metric. Our technique exploits the inherent redundancy of operand values across instructions by storing and reusing previously-computed results. Functional units are partitioned so that subunits operate on input subwords to generate output subwords that are combined to form the complete output word. We use a partitioned reuse cache which stores previously computed results for each functional subunit. The stored entries in the cache are compared against computed results of functional subunits to detect soft errors. We show that a partitioned reuse cache has a much better hit rate compared to a non-partitioned cache and it is possible to achieve SER reduction up to 51.87% in functional units with a power overhead of only 7.5%.