VLSI microprocessor architecture for a simplicial PWL function evaluation core

In this paper, we present a VLSI design for a piecewise linear (PWL) function evaluator. This design is based on a dedicated microprocessor architecture that allows re- programmability not only in the function, but also in the dimension (n = 1, . . . . , 6). The design was developed by using industry electronic design automation (EDA) tools and a standard CMOS 0.5 mum technology. Logic and analog simulations show the correct operation of the design.