Design and implementation of IP data reassembly processor for multimedia STB

This paper describes hardware-based IP data reassembly processor for multimedia STB (set-top-box) compatible with DVB-RCS. The conventional IP reassembly scheme is based on software processing of multimedia STB. As the transmission rate increases in order to support the broadband multimedia data services, the CPU load of multimedia STB is increased and reassembly performance is degraded. To provide smooth and flexible broadband multimedia data services, we proposed hardware based high speed reassembly processor. It has been tested and confirmed to meet required functions and performances.