A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs

In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening techniques in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based field-programmable gate arrays (FPGAs). The analytical method we developed allows an accurate study of the MCUs provoking domain crossing errors that defeat TMR. From our analysis we have found that most of the failures affect configurable logic block's routing resources. The experimental analysis has been performed on two realistic case study circuits. Experimental results are presented and discussed showing in particular that 2-bits MCUs may corrupt TMR 2.6 orders of magnitude more than single cell upsets (SCUs).