Predictive processing architecture extension for network processors

Increasing bandwidth requirements led to the introduction of network processors. Through the use of a multi-threading architecture, memory access latencies for table lookups, e.g. for routing and QoS support, can be hidden and throughput rates of 10 Gbit/s can be achieved by a single device. However, short end-to-end latencies which are essential for real-time applications are not targeted by this processing model. Instead of an fundamentally new architecture design, this paper comprises a mapping of an new processing model to commercial NPs. By its use in a multithreading architecture, a latency reduction of 12.5 % compared to traditional implementations can be achieved.