VHDL-AMS modeling of a multi-standard phase locked loop

The aim of this study is to provide a high-level VHDL-AMS model for multi-standard phase locked loop in SOI technology. The supported standards are GSM, GPS, DCS, Bluetooth, Wifi and WLAN. The model can be used to evaluate settling times, channel-to-channel transition times and also the timing needed to switch from one standard to another one. VCO noise, propagation time, transistors mismatch and slew rate and filter corner models are taken into account and their influences are evaluated.