RF design methodology for design-cycle-time reduction using parameterization of embedded passives on multilayer organic substrates

This paper presents an RF design methodology for reducing the design-cycle-time (DCT) using parameterization of embedded passive devices on multilayer organic substrates. Based on parameterized design libraries of embedded passive devices, designers can easily map ideal circuits into lossy circuits and physical layouts and use shunt parasitics of embedded inductors and capacitors, which results in design cycle time reduction. The proposed method was demonstrated through design of compact and highperformance bandpass filters on multilayer organic substrates by RF design experts and non-experts.