MVBLA based design of Constrained 1-bit Transform based motion estimation algorithm

In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform ME operation for a 2048×1152 pixel sized image frame at a speed of 20 frames/second.