Implementation of matrix-type FDTD algorithm on a graphics accelerator

This paper presents initial conclusions concerning the implementation of matrix-type FDTD algorithm on a low cost graphics accelerator (Nvidia GeForce GT 512 MB, 1.188 GHz) in CUDA (compute unified device architecture). Authors of this article pose a question as to whether using the graphics accelerator based on SIMD architecture (single instruction, multiple data) is reasonable in programming a matrix-type FDTD algorithm, then results of tests meant to compare the efficiency of sequential and parallel implementation are presented.