Observation and Utilization of Boron Segregation in Trench MOSFETs to Improve Figure of Merit (FOM)

We report the observation and utilization of boron segregation in trench MOSFETs (UMOS) to reduce on-resistance. A trenched LOCOS process has been applied to a UMOS structure to reduce the gate-to-source overlap capacitance (
C

_gs
), and it is observed that not only 40% reduction in
C

_gs
is achieved but also 45% reduction in specific on-resistance (
R

<sub>on,

sp</sub>
). Figure of merit is improved by 58%. TSUPREM-4 doping profile simulation at the silicon and oxide interface revealed the presence of boron segregation. On-resistance reduction is attributed by the shortened vertical channel length due to boron segregation.