Simulation study on the warpage behavior and board-level temperature cycling reliability of PoP potentially for high-speed memory packaging

PoP is a potential solution to high-speed memory packaging. For PoP package, warpage is known as a concern over package stacking and SMT yield [1]. The PoP package under current study has these features such as fine pitch which is 0.5mm for both top and bottom, small ball size and that most solder balls are located at the package’s two longer edges. Therefore the solder joint reliability (SJR) in Temperature Cycling on Board (TCoB) test may also pose a concern.. The current paper talks about the systematic simulation and optimization of warpage and TCoB SJR for DRAM PoP package. For warpage study, 3D finite element analysis (FEA) was performed. Not only room temperature warpage, but also reflow temperature warpage was investigated. Full factorial DOE analysis with approximation model determination was conducted for both material selection and structural optimization. Based on this study, material selection and layout design guidelines were quickly derived to optimize the warpage performance of this package. In SJR simulation study, various package and stacking configurations were proposed and simulated in an effort to improve the SJR in TCoB test. Suggestions for improvements were made based on those simulation results.