A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs

In this paper, we propose a novel architecture of a hybrid phase-locked loop (PLL) that does not require conventional analog filters. The architecture replaces the loop filter by an Incrementer/Decrementer (INC/DEC), a digital-to-analog converter (DAC) and a charge pump. The proposed solution helps alleviate many of the problems encountered with analog loop filters, which become more prominent as technology scales down. In order to prove the validity of the architecture, the design was implemented at the schematic level in 180nm TSMC CMOS technology. The design was simulated using SPECTRE in the Cadence’s Virtuoso analog environment, and results show that the proposed architecture performs as expected. When compared to an analog PLL with similar settling time, the proposed 180nm design even provides 1.8X better deterministic jitter.